R-Tile PCIe* Hard IP - R-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0, 4.0, and 5.0… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series R-Tile is a FPGA companion tile in Agilex™ 7 FPGA I-Series and M-Series devices that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass modes. PCIe 3.0, 4.0, and 5.0 configurations are natively supported. R-Tile also supports up to 16 SerDes channels through a PHY Interface for PCIe (PIPE) 5.1.1 in SerDes Architecture mode. PCI Express (IP) Aerospace ASIC Proto Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Wireless R-Tile PCIe* Hard IP Key Features Complete PCIe Protocol Stack in Hard IP – Full implementation of Transaction, Data Link, and Physical Layers with PIPE mode support. Offering Brief Yes No No Yes Encrypted Verilog Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Yes Yes Offering Brief Production a1JUi000004N5EPMA0 What's Included Encrypted Verilog Source Code Ordering Information No license required Direct a1JUi000004N5EPMA0 Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2025-10-24T17:24:30.000+0000 R-Tile is an FPGA companion tile that supports PCI Express* configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer (TL) Bypass modes. PCIe 3.0, 4.0, and 5.0 configurations are natively supported. Altera Solutions