Why does the software synthesize a very large number of logic levels for a for-loop in my design when an if-statement is nested in the loop? - Why does the software synthesize a very large number of logic levels for a for-loop in my design when an if-statement is nested in the loop? Description If your design contains a for-loop like this : integer i; for( i = ... ; ... ; ... ) begin a = expression of i ; if( ...... conditional statement about a ) begin statement; ...... end end The Intel® Quartus® Prime Pro Edition Software may synthesize a very large number of logic levels in this for-loop. Resolution If a for-loop contains these conditions then it cannot be optimized for logic depth an assignment expression that depends on the loop control variable an if statement nested in the loop which uses the assignment result as the select condition The assignment statement that depends on the loop control variable should be moved out of the for-loop block to enable further optimization. Once outside of the loop, the assignment statement can be converted to parallel assignments to each bit of a vector. Then the assignment result of each cycle can be indexed by the loop control variable in this newly created vector. The code can be modified as : vector[ N ] = ... ; ...... vector[ 2 ] = ... ; vector[ 1 ] = ... ; integer i ; for( i = ... ; ... ; ... ) begin if( ...... conditional statement about vector[i] ) begin statement; ...... end end The optimization is suitable for cases where the number of cycles is fixed and is not very large. The optimization may increase the usage of ALUTs while decreasing the number of logic levels. A future version of the Intel® Quartus® Prime Pro Edition Software is scheduled to optimize the original code automatically. Custom Fields values: ['novalue'] Troubleshooting 15011481191 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 21.4 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']