Connecting to the 28-nm Hard IP for PCI Express - 30 Minutes In this class, you will learn the signals that make up the various interfaces found on all of the Hard IP for PCI Express® IP cores versions and their uses. As a result, you will be able to connect those interfaces to your own Application Layer and control logic inside the FPGA so that you will be able to send and receive PCI Express packets as well as control and monitor the status of the PCI Express link. Targeted devices: Cyclone® V, Arria® V, and Stratix® V FPGAs Course Objectives At course completion, you will be able to: Understand the interfaces found on the Altera® Hard IP for PCI Express cores Connect the Altera® Hard IP for PCI Express to application layer and control logic in a design Skills Required Some understanding of the PCI Express Protocol specification is helpful, but not required Familiarity with common high-speed transceiver architecture OR viewing the following Transceiver Basics course OR attending the Building Gigabit Interfaces in Altera® Transceiver Devices Familiarity with FPGA/CPLD design flow Familiarity with the Quartus II design software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OPCICONNECT. FPGA_OPCICONNECT. <p>Connecting to the 28-nm Hard IP for PCI Express</p>