Why is there an unconstrained clock reported in the On-Chip Flash Intel® FPGA IP on Intel® MAX® 10? - Why is there an unconstrained clock reported in the On-Chip Flash Intel® FPGA IP on Intel® MAX® 10? Description An unconstrained clock is reported as shown below when using the On-Chip Flash Intel® FPGA IP on Intel® MAX® 10 : altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg Resolution This reported unconstrained path can be ignored as this is not a clock. Custom Fields values: ['novalue'] Troubleshooting 1506986933 False ['On-Chip Flash IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 18.1 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25