Conduit BFM and Tri-State Conduit BFM simulations fail when using the mixed simulation language option - Conduit BFM and Tri-State Conduit BFM simulations fail when using the mixed simulation language option Description The Altera® Conduit bus functional model (BFM) and Tri-State Conduit BFM do not generate a VHDL simulation model when the mixed simulation language option is selected. Simulations fail at the elaboration stage with the following error message: Error: (vsim-3059) Cannot connect a VHDL array signal to Verilog scalar port 'sig_fixedclk_locked'. Resolution If possible, you should disable the mixed simulation language option. Alternatively, you can edit the generated BFM signal declaration to use a bus signal type. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']