Does altering the FPGA IO standard actually change something in hardware? - Does altering the FPGA IO standard actually change something in hardware? Hello to the community. Here is a background/precondition of the question in the heading. I entered the realm of FPGA development using Verilog, DE10-Lite (MAX10 series) and Quartus Prime Lite Edition 20.1.1. My very first "program" was quite simple — three LEDs light one after another upon the button press. A running LED, if you please. For better understanding: OFF OFF OFF; Button pressed; ON OFF OFF; Button pressed; OFF ON OFF; Button pressed; OFF OFF ON; Button pressed; OFF OFF OFF; Here is Verilog code: module traffic(reset, clock, lights); input reset; input clock; output [2:0] lights; reg [2:0] lights; always @(posedge clock or negedge reset) begin if (!reset) begin lights = 3'h0; end else begin case (lights) 4'h0 : lights = 3'h1; 4'h1 : lights = 3'h2; 4'h2 : lights = 3'h4; 4'h4 : lights = 3'h0; default : lights = 3'h7; endcase end end endmodule The absolutely primitive program, and I was expecting it to work smoothly on the first try. Instead, it got stuck at step 5 mentioned above. Subsequent button presses have no impact on the state. The reset was fine, though. I was trying to defeat this issue in code for some time and had no success. So in the end, decided to assign the lights output to the different pins. Original ones were PIN_A7, PIN_A8 and PIN_A9, then they became PIN_B10, PIN_D13 and PIN_C13. And it started to work! After that, I tried to explicitly assign the IO standard to 3.3V LVTTL, like it is mentioned in the DE10-Lite User Manual and reverted to the original pins' assignments. And it began to work fine as well. It is obviously a problem with the logic levels or, more specifically, interpretation of the input voltage, but I can't get what exactly. I have studied the MAX10 GPIO User Guide hoping to find there exact description of how the IO standard handled at hardware level, but there is little information there. Just this diagram: It has nothing resembling an adjustable IO voltage, just a single Vccio. I have also asked the people at edaboard and they draw my attention to the fact that it is, in general, improper to use a button for clocking purposes due to bouncing, and that might be the root cause of my problem. And though I agree in general, I don't think it pertains to my case. Primarily because bouncing should trigger issues with an equal probability for all states, not for a sole one. Plus, there is a Schmitt trigger, at least the user manual mentions it: So my humble question is: " Can someone give me a hint or a link to the document describing how the IO standard is handled at the hardware level? ". To my surprise, this topic is not covered well enough either in docs I found or in forums. It feels like either everyone knows how it works or just relies on the software. Thanks in advance. Replies: Re: Does altering the FPGA IO standard actually change something in hardware? Thanks! Replies: Re: Does altering the FPGA IO standard actually change something in hardware? Yes, I've got that already. :-) The only thing I needed was the unambiguous answer to the question in the heading of the topic. Something like " Yes, there are some setup in the hardware, but we won't tell which exactly. Use the software! ". :-D Replies: Re: Does altering the FPGA IO standard actually change something in hardware? Hello, VCCIO if powering the IO banks of the IO , depending of where the IO is located. eg. If you power VCCIO -> 3.3V, the IO standard located in that IO bank should be 3.3V based IO. The IO assignment in Quartus pin planner must be aligned with the physical setup on your board. regards, Farabi Replies: Re: Does altering the FPGA IO standard actually change something in hardware? Right, this is the best place to ask Altera FPGA related questions. Replies: Re: Does altering the FPGA IO standard actually change something in hardware? Kindly thanks for your reply. It never hurts to ask a question at multiple resources. :-) Replies: Re: Does altering the FPGA IO standard actually change something in hardware? Hi, I believe I already explained here that the problem isn't related to IO-Standards rather than inappropriate clock source. (134) Does altering the FPGA IO standard actually change something in hardware? | Forum for Electronics You are specifically asking if changing the IO-Standard affects input signal processing. Short answer is, as long as you don't activate Schmitt Trigger or use a completely different IO type (e.g. voltage referenced or differential), it does not. Input threshold is a partly affected by actual bank voltage but less than proportianal for MAX10 series according to datasheet. An IOE description beyond the details given in Device Manual isn't publically available, I fear. Regards Frank