Why is the RAM: 2-Port FPGA IP created with a different byte-enable width than the value I set? - Why is the RAM: 2-Port FPGA IP created with a different byte-enable width than the value I set? Description Due to a problem with the Quartus® Prime Pro Edition Software version 23.1 and earlier, you might see the IP is created with a different byte-enable width than the one you configured in the Parameter Editor. Not all byte-enable widths are valid for all block types. If the memory block type is set as "Auto," the byte-enable width must still be valid for the block type used. For example for Arria® 10, Stratix® 10 and Agilex™ 7 devices these are the valid byte-enable widths MLAB: 5 or 10 M10K, M20K: 8, 9 or 10 Resolution To avoid this problem, ensure the byte-enable width is set to a valid width. Custom Fields values: ['novalue'] Troubleshooting 14019250634 False ['RAM 2-PORT IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 23.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']