In the 100GbE PHY IP Core, the CAUI-4 Design Example May Display Hold or Removal Timing Violations - In the 100GbE PHY IP Core, the CAUI-4 Design Example May Display Hold or Removal Timing Violations Description The CAUI-4 variant of the 100GbE PHY IP core may display hold or removal timing violations when compiled with the 12.1 release of the Quartus II software because certain clocks are not promoted to global clocks. Setting the Quartus II software assignment AUTO_GLOBAL_CLOCK to ON may promote the clocks, but can result in setup timing failures due to issues with clock buffer placement. Explicitly forcing the placement of the clock buffers may solve this issue. Resolution This issue has no workaround. This issue is fixed in version 13.0 of the 100GbE PHY IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']