SoC Designs With HPS Memory Interface and FPGA Memory Controller on Cyclone V Devices Can Encounter Error - SoC Designs With HPS Memory Interface and FPGA Memory Controller on Cyclone V Devices Can Encounter Error Description This problem affects DDR2, DDR3, and LPDDR2 products. A design targeting a Cyclone V device, with both an HPS memory interface and an FPGA hard or soft memory controller, can encounter an error due to a limitation in the pin_assignments.tcl script. If the HPS pin_assignments.tcl script is run before the FPGA pin_assignments.tcl , the I/O assignment for the RZQ pin on the HPS can be overwritten by the FPGA script, resulting in an error message similar to the following: Error (175001): Could not place pin Info (175028): The pin name: <your_design_name>_hps_oct_rzqin Error (184016): There were not enough single-ended input pin locations available (5 locations affected) Resolution The workaround for this issue is to manually change the I/O standard assignment for the HPS RZQ pin to SSTL-15 CLASS I after running the pin_assignments.tcl for both interfaces. This issue will be fixed in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']