Agilex5 GTS Reset Sequence - Agilex5 GTS Reset Sequence I am looking to use the GTS reset sequencer to enable the GTS PMA/FEC Direct PHY. In the docs, there are these diagrams: For this, I have designed the following component (which I have also tried with ~system_reset): always @(posedge system_clk_100) begin if (system_reset) begin gts_i_tx_reset <= 1'b1; gts_i_rx_reset <= 1'b1; end else begin if((gts_o_tx_reset_ack==1'b1) && (gts_o_rx_reset_ack==1'b1) && (gts_o_tx_pll_locked==1'b0) && (gts_o_tx_ready==1'b0) && (gts_o_rx_ready==1'b0)) begin gts_i_tx_reset <= 1'b0; gts_i_rx_reset <= 1'b0; end end end However, it seems my board is still stuck in reset: Filename 'fpga/soc_system_base.rbf'. Load address: 0x90000000 Loading: ################################################################# ################################################################# ####### 2 MiB/s done Bytes transferred = 1998848 (1e8000 hex) .............................................................FPGA reconfiguration failed! Command 'load' failed: Error -110 FPGA not ready. Bridge reset aborted! And I believe it may be due to this. Does this design look ok? Or should I look elsewhere for the root of the issue? Thanks! Replies: Re: Agilex5 GTS Reset Sequence Hi, I believe you may have opened a new thread for our configuration specialist to provide further assistance. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you very much. Replies: Re: Agilex5 GTS Reset Sequence Hi, Thank you for your update. From what I understand, you’re also observing the FPGA configuration issue when using the JTAG configuration method. I believe it would be helpful to engage our configuration specialist for further assistance. Would you mind opening a new thread specifically for this potential configuration-related issue? This will allow our configuration specialist to review and provide more targeted support. In the meantime, it may be useful to check the configuration-related status signals—such as NCONFIG, CONF_DONE, NSTATUS, and INIT_DONE—and share their behavior in the new thread. This information could help the specialist in diagnosing the issue more effectively. Please let me know if you have any concerns or need further assistance. Thank you! Best regards, Chee Pin Replies: Re: Agilex5 GTS Reset Sequence Hi in fact the same issue is occurring with the JTAG boot Replies: Re: Agilex5 GTS Reset Sequence Hi, Referring back to your initial observation that suggests a possible FPGA configuration failure, I believe it’s important to isolate this issue first. Would you be able to try programming the device directly via JTAG to confirm whether the FPGA can be successfully configured? From my understanding, the XCVR reset typically does not impact FPGA configuration, as the transceiver logic only starts operating after a successful configuration. Unless the message “FPGA reconfiguration failed” is referring to something else (e.g., a soft reconfiguration or user logic indication), it may not be a true configuration failure. Please let me know if you have any concerns or need further assistance. Thank you! Best regards, Chee Pin Replies: Re: Agilex5 GTS Reset Sequence Thanks! This is reflected now in the recent post Replies: Re: Agilex5 GTS Reset Sequence Hi @CheePin_C_Intel ! Thanks for your response I will try to answer: 1: The following is my qsys design: ... // GTS signals wire gts_i_rx_cdr_refclk; wire gts_i_tx_pll_refclk; reg gts_i_tx_reset, gts_i_rx_reset; wire gts_o_tx_reset_ack, gts_o_rx_reset_ack; wire gts_i_tx_coreclkin, gts_i_rx_coreclkin; wire gts_o_tx_clkout, gts_o_rx_clkout; wire gts_o_tx_serial_data, gts_o_tx_serial_data_n; wire gts_i_rx_serial_data, gts_i_rx_serial_data_n; wire [79:0] gts_i_tx_parallel_data; wire [79:0] gts_o_rx_parallel_data; wire osc_clk; wire osc_rst; wire [31:0] osc_pattern_o; wire raw2s_clk; wire raw2s_rst; wire [31:0] raw2s_data_i; assign gts_i_tx_coreclkin = gts_o_tx_clkout; assign gts_i_rx_coreclkin = gts_o_rx_clkout; //assign gts_i_tx_parallel_data[38] = 1'b0; // TX PMA Interface Data Valid assign gts_i_tx_parallel_data[31:0] = osc_pattern_o; assign raw2s_data_i = gts_o_rx_parallel_data[31:0]; assign gts_i_rx_serial_data = gts_o_tx_serial_data; assign gts_i_rx_serial_data_n = gts_o_tx_serial_data_n; always @(posedge system_clk_100) begin if (system_reset) begin gts_i_tx_reset <= 1'b1; gts_i_rx_reset <= 1'b1; end else begin if((gts_o_tx_reset_ack==1'b1) && (gts_o_rx_reset_ack==1'b1)) begin gts_i_tx_reset <= 1'b0; gts_i_rx_reset <= 1'b0; end end end //// Oscillator assign osc_clk = gts_o_tx_clkout; assign osc_rst = system_reset; // Qsys Top module qsys_top soc_inst ( ... .intel_directphy_gts_1_i_rx_cdr_refclk_p_clk (REFCLK), .intel_directphy_gts_1_i_tx_pll_refclk_p_clk (REFCLK), .intel_directphy_gts_1_i_tx_reset_tx_reset (gts_i_tx_reset), .intel_directphy_gts_1_i_rx_reset_rx_reset (gts_i_rx_reset), .intel_directphy_gts_1_o_tx_reset_ack_tx_reset_ack (gts_o_tx_reset_ack), .intel_directphy_gts_1_o_rx_reset_ack_rx_reset_ack (gts_o_rx_reset_ack), .intel_directphy_gts_1_i_tx_coreclkin_clk (gts_i_tx_coreclkin), .intel_directphy_gts_1_i_rx_coreclkin_clk (gts_i_rx_coreclkin), .intel_directphy_gts_1_o_tx_clkout_clk (gts_o_tx_clkout), .intel_directphy_gts_1_o_rx_clkout_clk (gts_o_rx_clkout), .intel_directphy_gts_1_o_tx_serial_data_o_tx_serial_data (gts_o_tx_serial_data), .intel_directphy_gts_1_o_tx_serial_data_n_o_tx_serial_data_n (gts_o_tx_serial_data_n), .intel_directphy_gts_1_i_rx_serial_data_i_rx_serial_data (gts_i_rx_serial_data), .intel_directphy_gts_1_i_rx_serial_data_n_i_rx_serial_data_n (gts_i_rx_serial_data_n), .intel_directphy_gts_1_i_tx_parallel_data_i_tx_parallel_data (gts_i_tx_parallel_data), .intel_directphy_gts_1_o_rx_parallel_data_o_rx_parallel_data (gts_o_rx_parallel_data), .intel_srcss_gts_1_i_src_rs_priority_src_rs_priority (1'b1), .oscillator_0_clk_clk (osc_clk), .oscillator_0_rst_reset (osc_rst), .oscillator_0_oscillator_pattern_o_new_signal (osc_pattern_o), .raw_to_stream_1_raw_data_in_i_new_signal (raw2s_data_i), ... ); ... I then generate the HDL, and compile the bitstream - and load over TFTP. 2: Using this devkit 3: This is not an example design generated from Quartus - I am having trouble there too (different thread for that topic) Replies: Re: Agilex5 GTS Reset Sequence Hi, Just to add on, you may consider simplifying your reset release condition by making it dependent solely on o_tx_reset_ack and o_rx_reset_ack. These two signals indicate that the TX and RX paths are fully reset, which may help streamline your logic. Thanks! Replies: Re: Agilex5 GTS Reset Sequence Hi, Sorry for the delay. As I look at your reset codes, there seems to be no anomaly with the de-assertion following the timing diagram. To ensure we are on the same page, just would like to check with you on the following: 1. I notice that your printout seems to mention about "FPGA reconfiguration failed". As I understand it, XCVR reset is generally not directly affecting the FPGA configuration. Would you mind to further elaborate on the steps taken to get to this error? 2. Just wonder if you are using any Altera devkit? 3. Just to check if you are using any example design generated from Quartus? If yes, please let me know the specific design that you are using. Thank you. Replies: Re: Agilex5 GTS Reset Sequence Hi, Thank you for filing this case and sharing the details. As I understand it, you have some inquiries related to the GTS XCVR reset sequence. Please allow me some time to review the information, and I’ll get back to you as soon as possible.