Creating a System Design with Platform Designer: Finish the System - Same Course in Simplified Chinese: 使用Platform Designer创建系统设计:完成系统 35 Minutes This training is part 2 of 2. The Platform Designer system integration tool, formerly known as Qsys, saves design time and improves productivity by automatically generating interconnect logic to connect intellectual property (IP) functions and subsystems. In this training, you'll finish the system by making connections between component interfaces, setting up base addresses for memory-mapped slaves, and reviewing the system design. You'll then generate the system HDL files and incorporate the design in the Quartus® Prime software FPGA design flow. This training includes a lab exercise with instructions and files that are designed for the Quartus® Prime software, version 17.1, and the Terasic Cyclone® V GX starter kit. Course Objectives At course completion, you will be able to: Create a system design in the Platform Designer user interface Incorporate your Platform Designer system into an Quartus® Prime project for compilation Skills Required Familiarity with FPGA/CPLD design flow Working knowledge of the Quartus® Prime software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OQSYSFINISH. FPGA_OQSYSFINISH. <p>Creating a System Design with Platform Designer: Finish the System</p>