Why do I see an error message stating "device requires the DEVICE_INITIALIZATION_CLOCK option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ" when compiling the F-Tile Low Latency Ethernet 10G MAC FPGA IP Design Example? - Why do I see an error message stating "device requires the DEVICE_INITIALIZATION_CLOCK option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ" when compiling the F-Tile Low Latency Ethernet 10G MAC FPGA IP Design Example? Description Due to a problem in the F-Tile Low Latency Ethernet 10G MAC FPGA IP, the generated F-Tile Low Latency Ethernet 10G MAC FPGA IP Design Example will fail to compile, with the following Error Message. Error(22849): FPGA IP instantiated in the design requires the DEVICE_INITIALIZATION_CLOCK option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ or OSC_CLK_1_125MHZ. This assignment is missing in the Quartus Setting File (*.qsf file). Resolution To work around this problem, update the generated Quartus Setting File (*.qsf file) for the F-Tile Low Latency Ethernet 10G MAC FPGA IP Design Example with the constraints " set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_100MHZ " manually and re-run the compilation. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.1. Custom Fields values: ['novalue'] Troubleshooting 16022676343 False ['Low Latency Ethernet 10G MAC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']