How can I create VHDL for a byte-enabled true dual-port RAM to enable correct inference during Quartus II synthesis and correct behavior during RTL simulation? - How can I create VHDL for a byte-enabled true dual-port RAM to enable correct inference during Quartus II synthesis and correct behavior during RTL simulation? Description Due to a problem in the Quartus® II software versions 11.0 and earlier, the Byte-enabled True Dual Port RAM VHDL template does not correctly infer a RAM megafunction in the Quartus II synthesis and does not simulate correct behavior in RTL simulation. To work around this problem, make the following changes in the Byte-enabled True Dual Port RAM VHDL template: Change the declaration of ram from signal to shared variable . Add the following lines after the declaration of ram : attribute ramstyle : string; attribute ramstyle of ram : variable is "no_rw_check"; Change the operator for all assignments to ram from <= to := . Download a version of the template with the necessary changes from the following link: byte_enabled_true_dual_port_ram.vhd The Byte-enabled True Dual Port RAM VHDL template is scheduled to be fixed in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Simulation'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']