Should I set the test_in bus to 0 as described in the Test Interface Signals sections of the IP Compiler for PCI Express User Guide? - Should I set the test_in bus to 0 as described in the Test Interface Signals sections of the IP Compiler for PCI Express User Guide? Description This is an error in the document. Do not do this. Resolution Intel recommends setting test_in = 0x3A8 for hardware, or 0x3A9 for simulation. Custom Fields values: ['novalue'] Troubleshooting - False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® IV GX FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']