Why is the tRTP timing parameter box missing from the Intel® Stratix® 10 and Intel Arria® 10 EMIF IP GUIs? - Why is the tRTP timing parameter box missing from the Intel® Stratix® 10 and Intel Arria® 10 EMIF IP GUIs? Description The tWR and tRTP parameters share the same DDR4 MR0 mode register bits. Once the tWR parameter is set, the tRTP parameter is set automatically because the tWR and the tRTP relationship is fixed. Resolution None Custom Fields values: ['novalue'] Troubleshooting FB: 531779 127216; False ['External Memory Interfaces Arria® 10 FPGA IP', 'External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 17.1 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']