Why does the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* fails to receive VirtIO Transaction Level Packets? - Why does the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* fails to receive VirtIO Transaction Level Packets? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the address decoding of the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* may fail when receiving a VirtIO Transaction Level Packet (TLP), causing the TLP to be ignored. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.2. Custom Fields values: ['novalue'] Errata 15011065611 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 22.1 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']