Why are there FCS errors seen in the F-Tile 25G Ethernet IP when using the Quartus® Programmer version 23.3 and onward? - Why are there FCS errors seen in the F-Tile 25G Ethernet IP when using the Quartus® Programmer version 23.3 and onward? Description The FCS errors are reported in the F-Tile 25G Ethernet IP when using the Quartus® Programmer version 23.3 and onward. This problem is caused by the FIFO pointers not having a decent gap between read and write pointers. During the traffic test, FCS errors are seen due to random empty read signals during the packet transactions. Resolution The workaround is to modify RTL logic to gate the read enable signal for TX and RX FIFOs and give a decent gap between read and write pointers. Also, the FIFO depth must be reduced from 128 to 16, and the FIFO's reset logic must be modified to handle the latency between read and write pointers when they are out of reset. This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 24.3. Custom Fields values: ['novalue'] Troubleshooting 15016111048 False ['F-Tile 25G Ethernet Soft-IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']