Why does the CSR access data width of R-Tile Intel® FPGA IP for Compute Express Link* (CXL*) Design Example mismatch the function in the software driver? - Why does the CSR access data width of R-Tile Intel® FPGA IP for Compute Express Link* (CXL*) Design Example mismatch the function in the software driver? Description Due to a problem in Intel® Quartus® Prime Pro Edition Software version 23.2 and later, the CSR access data width is changed from 32bit to 64bit in R-Tile Intel® FPGA IP for Compute Express Link* (CXL*) Type2/3 Design Example; this causes a mismatch between software driver function and user CSR logic design. Resolution This problem is not planned to be fixed in future releases of the Intel® Quartus® Prime Edition Software. To work around this problem, refer to the f ollowing code example: 1. Open /hardware_test_design/common/ex_default_csr/ex_default_csr_avmm_slave.sv 2. Implement the CSR with a 64-bit data width rather than the standard 32-bit data width. //64bit data width always @(posedge clk ) if (!reset_n) begin ats_stu <= 5'b0; ats_en <= 1'b0; ptm_eg <= 8'b0; ptm_rs <= 1'b0; ptm_en <= 1'b0; end else if (write && config_access)begin case(address[20:0]) 21'h00E00 : begin ats_stu <= writedata[60:56]; ats_en <= writedata[63]; end 21'h00E18 : begin ptm_eg <= writedata[15:8]; ptm_rs <= writedata[1]; ptm_en <= writedata[0]; end default ; endcase end //Read logic always @(posedge clk ) if (!reset_n) begin cfg_readdata <= 64'h0; end else if(read&&config_access)begin case(address[20:0]) 21'h00E00 : cfg_readdata <= {{ats_en,10'b0,ats_stu,16'h0020},EX_CAP_HEADER_ATS }; // 21'h00E04 : cfg_readdata <= {{ats_en,10'b0,ats_stu,16'h0020},32'b0} ; 21'h00E10 : cfg_readdata <= {EX_CAP_HEADER_PTM_CAP,EX_CAP_HEADER_PTM}; // 21'h00E14 : cfg_readdata <= {EX_CAP_HEADER_PTM_CAP,32'b0}; 21'h00E18 : cfg_readdata <= {32'b0 ,{16'h0,ptm_eg,6'h0,1'b0,ptm_en}}; default : cfg_readdata <= {32'b0 ,32'hffff_ffff }; endcase end else begin cfg_readdata <= 64'h0; end Custom Fields values: ['novalue'] Troubleshooting 15014201756 False ['R-Tile for Compute Express Link Solution'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']