Why we see EMAC A setting changing from RMII to RGMII on Pin Mux GUI in Intel Agilexl® 7 FPGA HPS IP? - Why we see EMAC A setting changing from RMII to RGMII on Pin Mux GUI in Intel Agilexl® 7 FPGA HPS IP? Description Due to a visual problem in the Intel® Quartus® Prime Pro Edition Software, we might see EMAC A setting change from RMII to RGMII in Intel Agilex® 7 FPGA HPS IP Pin Mux GUI when clicking the other IP in the Platform Designer and back. Resolution The RMII interface setting is valid, and we can reference the Advanced IP Placement for the RMII interface I/O assignment. Custom Fields values: ['novalue'] Troubleshooting 1508220302 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 20.1 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['novalue']