Arria V GZ Hard IP for PCI Express IP Core RX Interface Not in High Impedance when PERST Is Asserted - Arria V GZ Hard IP for PCI Express IP Core RX Interface Not in High Impedance when PERST Is Asserted Description When the nPERSTL* pin is holding the Arria V GZ Hard IP for PCI Express IP Core in reset, the RX interface is not in high impedance. Instead, the RX interface shows about 1K ohm impedance. If the link partner performs receiver detect at this time, it might be able to detect some receiver lanes. If the link partner does not detect all lanes, when the Hard IP exits reset and begins link training, the link may downtrain. And, the link may exclude some lanes that are actually available. Resolution The workaround is to select the CMU PLL and the hard reset controller for Gen2 variants of the Arria V GZ Hard IP for PCI Express IP Core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']