Agilex™ 3 SoC Hard Processor System (HPS) Overview - 26 Minutes The Agilex™ 3 FPGA product family extends the innovations of the Agilex FPGA portfolio to low-power and cost-optimized FPGA applications. The Agilex 3 FPGAs and SoCs serve a broad range of applications that require higher performance, lower power consumption, small form factor, and lower logic densities. Agilex 3 FPGAs bring the high-performance Hyperflex® FPGA architecture to power and cost-optimized applications. It offers up to 2.8 peak INT8 TOPS with FPGA AI Suite support to enable push-button flow from industry standard frameworks to FPGA bitstream. AI-optimized DSPs with tensor blocks and hardened IP blocks deliver robust capabilities in a single chip while supporting dual Arm*-Cortex* A55 cores. In this eLearning, you will be introduced to the Hard Processor System features of the Agilex 3 SoC FPGAs. Course Objectives At course completion, you will be able to: Understand the basic features of Agilex™ 3 FPGA and SoCs Explore the Hard Processor System (HPS) architectures across different Altera® SoC FPGA families Compare the key features of Agilex™ HPS against prior Altera SoC FPGA families Skills Required Basic knowledge of Digital System design Basic knowledge of the Microprocessor Unit General understanding of FPGA architecture Basic understanding of Quartus® Prime Design Software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OAG3HPS. FPGA_OAG3HPS. <p>Agilex 3 SoC Hard Processor System (HPS) Overview</p>