How should I connect the Reset Input Ports of Altera Dual Clock FIFOs? - How should I connect the Reset Input Ports of Altera Dual Clock FIFOs? Description Altera provides highly configurable FIFO implementations. In FIFO implementations that have a separate clock for the data input (Slave, Sink, Receiver) and the data output (Master, Source, Sender) interfaces, the corresponding resets for each clock domain must be asserted at the same time. This ensures that the internal input data pointers and output data pointers are aligned after reset deassertion. The Altera components that implement a dual clock FIFO are: Avalon-MM Clock Crossing bridge Avalon-ST Dual Clock FIFO Avalon FIFO Memory Resolution In order to reset both data input and data output sides of dual clock FIFOs that have two reset inputs, each reset input port should be connected to the same reset source. The following list shows which reset input ports for which components should be connected to the same reset source: For the Avalon-MM Clock Crossing bridge, connect these inputs to the same reset source: m0_reset s0_reset For the Avalon-ST Dual Clock FIFO, connect these inputs to the same reset source: in_clk_reset out_clk_reset For the Avalon FIFO Memory, connect these inputs to the same reset source: reset_in reset_out This information is scheduled to be included in a future release of the Quartus II handbook. Custom Fields values: ['novalue'] Troubleshooting novalue False ['Reset'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']