Why does the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example generation completed with errors? - Why does the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example generation completed with errors? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3, the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example cannot be generated successfully. Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software version 21.3. Download and install the patch in this KDB article. Intel® Quartus® Prime Pro Edition Software v21.3 Patch 0.06 for Windows (.exe) Intel® Quartus® Prime Pro Edition Software v21.3 Patch 0.06 for Linux (.run) Readme for Intel® Quartus® Prime Pro Edition Software v21.3 Patch 0.06 (.txt) This patch is scheduled to be included in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15010156371 True ['IP Low Latency 10-Gbps Ethernet MAC and PHY Function IP-10GEUMAC'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.4 21.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']