Why does VCS* simulation fail for the example design testbench of the 25G Ethernet Intel® Stratix® 10 FPGA IP variant with PTP, RSFEC, and VHDL options chosen? - Why does VCS* simulation fail for the example design testbench of the 25G Ethernet Intel® Stratix® 10 FPGA IP variant with PTP, RSFEC, and VHDL options chosen? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.3 and earlier, the VCS* simulation of the example design’s testbench of the 25G Ethernet Intel® Stratix® 10 FPGA IP variant with PTP, RSFEC, and VHDL options chosen will fail in VCS with “Cross-module reference resolution error.” Resolution To work around this problem perform the following steps: 1.) Navigate to the example design’s “example_testbench/” directory 2.) Open the “basic_avl_tb_top.sv” file 3.) Comment out line 40: defparam singleport1588_s10gxt_inst.s10_top.alt_e25s10_0.SIM_SHORT_AM = 1'b1; 4.) Recompile the simulation Custom Fields values: ['novalue'] Troubleshooting 1409801094 True ['25G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.3 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-23