Why does H2F interface data width in simulation file not match the data width set in HPS IP in the Platform Designer for Intel Agilex® 7 device? - Why does H2F interface data width in simulation file not match the data width set in HPS IP in the Platform Designer for Intel Agilex® 7 device? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 and earlier, when you set H2F data width to 128 bit in HPS IP for Intel Agilex® 7 device in the Platform Designer and generate the system, you will find the S2F_DATA_WIDTH is set to wrong value (0) in the generated simulation file. Resolution The problem has been fixed in the Intel® Quartus® Prime Pro Edition Software version 23.2. Custom Fields values: ['novalue'] Troubleshooting 15013041638 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.2 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']