40GbE IP Core Locks Up or Sends Incorrect Packets if SOP or EOP is Asserted While Valid is Not Asserted on the Avalon-ST TX Client Interface - 40GbE IP Core Locks Up or Sends Incorrect Packets if SOP or EOP is Asserted While Valid is Not Asserted on the Avalon-ST TX Client Interface Description If user logic asserts the l4_tx_startofpacket or l4_tx_endofpacket signal on the Avalon-ST client interface of a 40GbE IP core while not asserting l4_tx_valid , the IP core could: Lock up, or Send incorrect packets to the Ethernet link. Resolution To avoid this issue, ensure you gate the l4_tx_startofpacket and l4_tx_endofpacket signals with the l4_tx_valid signal in your 40GbE design. This issue is fixed in version 15.0 Update 1 of the 40-100GbE IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 15.0.1 15.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25