Link Training Issues May Occur with Stratix V Hard IP for PCIe Gen2 Endpoints in Gen3 Systems - Link Training Issues May Occur with Stratix V Hard IP for PCIe Gen2 Endpoints in Gen3 Systems Description Link training issues may occur with Stratix V Hard IP for PCIe Gen2 Endpoints in Gen3 systems, such as the Intel Ivy Bridge or Sandy Bridge microprocessors. Resolution The workaround is to upgrade to the Quartus II 12.0 SP2 software release. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0.2 11.0 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']