Why can't I use systolic mode when addnsub is used? - Why can't I use systolic mode when addnsub is used? Description In the MAC and mult_adder cores, when the addnsub signal is used, the systolic register can't be used properly. Resolution This is due to the hardware limitation of the 28nm DSP block structure. The Systolic is not the typical Systolic structure. Thus when the addnsub is toggled dynamically, the calculation result will be incorrect for the first tap result. So, please don't put this support into the megacore. Custom Fields values: ['novalue'] Troubleshooting 1408026098 False ['DSP Builder for Pro Edition IPT-DSPBUILDER'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']