Warning (332056): PLL cross checking found inconsistent PLL clock settings - Warning (332056): PLL cross checking found inconsistent PLL clock settings Description You may encounter the above warning when compiling the XAUI PHY IP using Quartus® II software version 13.1 for Arria ® V, Cyclone ® V, and Stratix ® V transceiver devices. This is due to missing SDC constraints for the XAUI PHY IP clocks. Resolution To fix this problem, add the following SDC constraints for the XAUI PHY IP clocks before running the compilation: create_clock -period <value> -name <clock_name> [get_ports pll_ref_clk] create_clock -period <value> -name <clock_name> [get_ports phy_mgmt_clk] derive_pll_clocks Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']