Stratix V Pin-Out Table: Known Issues - Stratix V Pin-Out Table: Known Issues Description Issue 63753: Pin out tables for all Stratix V devices dated July 2012 and earlier The pin out files do not show that DCLK can be used as a user I/O after configuration when the configuration mode is an Active mode. DCLK can be used as a regular I/O pin after configuration when the configuration mode is an Active mode Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']