Can the Intel Agilex® 7 FPGA EMIF Debug Toolkit support interfaces in two different I/O rows? - Can the Intel Agilex® 7 FPGA EMIF Debug Toolkit support interfaces in two different I/O rows? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.1, the Intel Agilex® 7 FPGA EMIF Debug Toolkit cannot support interfaces in two different I/O rows since it cannot distinguish between interfaces with the same ID which are in different rows. In an Intel Agilex FPGA EMIF design, the ID cannot be set manually. Note: The Intel Agilex FPGA EMIF Debug Toolkit can support multiple interfaces in one I/O row. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 20.1, enable the Intel Agilex® 7 FPGA EMIF Debug Toolkit on interfaces implemented in one I/O row at a time. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.2. Custom Fields values: ['novalue'] Troubleshooting 14011314466 False ['External Memory Interfaces Debug Component IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.2 20.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']