What does the per lane information seen in the P-Tile Debug Toolkit tab correspond to ? - What does the per lane information seen in the P-Tile Debug Toolkit tab correspond to ? Description You can see the per-lane information under each tab in the P-Tile Debug Toolkit. In the Configuration Space tab, there is the logical lanes information for each port In the C hannels Parameter tab, there is the physical lanes information for each port In the Eye Viewer Controls tab, there is the physical lanes information for each port Resolution This information is added to the P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express User Guide starting with v21.4 onwards. Custom Fields values: ['novalue'] Troubleshooting 14015596775 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.4 21.3 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-05