I compiled my design and it worked in the lab. Ive re-compiled the same RTL in the same version of Quartus® II software and it doesnt work. What could be wrong? - I compiled my design and it worked in the lab. Ive re-compiled the same RTL in the same version of Quartus® II software and it doesnt work. What could be wrong? Description Check the following common trouble areas which can affect a design that can be impacted by marginal changes: Analog Phenomenon: · Power & ground not within specification · Insufficient decoupling · Noise / Signal Integrity Timing Constraints · Incomplete constraints · Inaccurate constraints · Poor timing exception constraints Improper handling of async interfaces · Use Design Assistant to verify your design – You can find useful information to help resolve problems · Reset structures · Asynchronous clock domain transfers · Asynchronous signals Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® III FPGAs'] ['novalue'] ['novalue'] ['novalue']