Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings - Error(21842): Support logic cannot be generated because IP components used in the design have conflicting settings Description Due to a problem in the Quartus® Prime Pro Edition Software, you might see the Quartus® Support-Logic Generation stage error when inverting Agilex™ 7 device F-Tile TX or RX FHT channels. The Quartus® Prime Pro Edition Software expects both TX and RX FHT channels to be inverted at the same time. Example QSF assignments for TX & RX P/N inversion are: set_instance_assignment -name HSSI_PARAMETER "tx_invert_p_and_n=<parameter_value>" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "rx_invert_p_and_n=<parameter_value>" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> Resolution To work around this problem you can add an additional QSF assignment that disables the loopback mode of the FHT channel you want to invert. An example QSF assignment that disables F-Tile FHT channel loopback is shown below: set_instance_assignment -name HSSI_PARAMETER "loopback_mode=LPBK_DISABLED" -to <SERIAL_PIN> -entity <TOP_LEVEL_NAME> Custom Fields values: ['novalue'] Troubleshooting 15015555035 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 23.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']