Why do I see errors when compiling the DDR3 UniPHY-based controller with HPS in the Platform Designer? - Why do I see errors when compiling the DDR3 UniPHY-based controller with HPS in the Platform Designer? Description You might see the following errors during the Analysis & Synthesis compilation stage for DDR3 UniPHY-based controllers with hard processor system (HPS) in the Platform Designer: Error: Input port DATAIN on atom "{hierarchy}.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured Info (129003): Input port DATAIN is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal Error: Input port ENA on atom "{hierarchy}.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured Info (129003): Input port ENA is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal Error: Input port UPDATE on atom "{hierarchy}.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured Info (129003): Input port UPDATE is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal Resolution This problem occurs when using deferred generation of the Platform Designer, where the DDR3 controller is generated on-the-fly during compilation. The correct method to properly compile the design is as follows: Create the Platform Designer system. In the Platform Designer system, generate the DDR3 controller IP. Include the resulting .qip file into your project files and not the .qsys file. Custom Fields values: ['novalue'] Troubleshooting 1408013872 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']