Warning (11106): Shared VREF is used as GPIO <pin name&gt. This action reduces fmax performance. - Warning (11106): Shared VREF is used as GPIO <pin name&gt. This action reduces fmax performance. Description VREF pins have a high pin capacitance than other pins in devices that support dual-purpose VREF pins. Avoid using the VREF pins as an I/O pin of a bus or clock function because the higher capacitance will slow the edge rates and affect I/O timing. Resolution Related Articles Is there a longer delay on VREF pins when used as I/O compared to general purpose I/O pins in Cyclone-series devices that support dual-purpose VREF pins? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']