Why does preforming read and write data via FPGA to HPS bridge fail when SMMU is enabled in HPS IP? - Why does preforming read and write data via FPGA to HPS bridge fail when SMMU is enabled in HPS IP? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 release and earlier, the Agilex™ 5 HPS FPGA to HPS bridge could not be accessed by the FPGA Fabric when SMMU is enabled. Resolution This problem is resolved in Quartus® Prime Pro Edition Software v24.3.1. Custom Fields values: ['novalue'] Troubleshooting 15016780422 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']