In Intel® Stratix® 10 TX and MX device how should the VCCIO_HPS and VCCPLL_HPS power pins be connected when not using HPS? - In Intel® Stratix® 10 TX and MX device how should the VCCIO_HPS and VCCPLL_HPS power pins be connected when not using HPS?
Description If you do not intend to use the HPS in an Intel® Stratix® 10 TX and MX device, you must still provide power to the VCCIO_HPS and VCCPLL_HPS pins. Do not leave the VCCIO_HPS and VCCPLL_HPS power pins floating or connect them to GND. Resolution N/A
Custom Fields values:
['novalue']
Troubleshooting
595813; 2205894334
False
['novalue']
['novalue']
novalue
novalue
['Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA']
['novalue']
['novalue']
['novalue'] - 2023-01-27
external_document