Error (175020): The Fitter cannot place logic IO_LANE that is part of Generic Component ed_synth_phylite_s20_0_example_design, to which it is constrained, because there are no valid locations in the region for logic of this type - Error (175020): The Fitter cannot place logic IO_LANE that is part of Generic Component ed_synth_phylite_s20_0_example_design, to which it is constrained, because there are no valid locations in the region for logic of this type Description Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 20.4, you may encounter a fitter issue while placing REFCLK sharing between IO48 tiles within the same banks in PHY Lite Interfaces Intel Agilex® 7 FPGA IP. Resolution These errors are due to a hardware limitation. The fitter didn't check the REFCLK location constraint because it assumes the REFCLK needs to be in the same tile. Custom Fields values: ['novalue'] Troubleshooting 14012814984 False ['External Memory Interfaces (EMIF) IP'] ['FPGA Dev Tools Quartus® Prime Software'] 20.4 20.4 ['Agilex™ FPGA Portfolio'] ['novalue'] ['novalue'] ['novalue']