Any top or bottom central PLL in Stratix V ES devices that has its reference clock fed by a clock network should not be fed a clock faster than 400 MHz - Any top or bottom central PLL in Stratix V ES devices that has its reference clock fed by a clock network should not be fed a clock faster than 400 MHz Description Any top or bottom central PLL in Stratix V ES devices that has its reference clock fed by a clock network should not be fed a clock faster than 400 MHz. Resolution If possible, directly feed the reference clock from a pin or manually place the PLL on the left or right side. Custom Fields values: ['novalue'] Troubleshooting novalue True ['PLL'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']