Why isn't the calibration busy status signal de-asserted after user recalibration is enabled for Intel® Stratix® 10 device? - Why isn't the calibration busy status signal de-asserted after user recalibration is enabled for Intel® Stratix® 10 device? Description You may find calibration busy status keep asserted when enabling user calibration for Intel® Stratix® 10 device. Resolution During user recalibration with the reconfiguration interface, if the reconfig_write signal is pulled high for multiple clock cycles after the reconfig_waitrequest is de-asserted, the calibration busy indicator, which is either tx_cal_busy, rx_cal_busy or pll_cal_busy signal will be found not de-asserted later. Then it will lead to transceiver stalling. Follow the waveform of writing to the reconfiguration interface in Intel® Stratix® 10 L- and H-Tile user guide; the reconfig_write should be only one clock cycle high during every writing process after the reconfig_waitrequest is de-asserted. If you'd like to use calibration enable registers, please follow the rules strictly to avoid unexpected calibration busy indicator behavior. Custom Fields values: ['novalue'] Troubleshooting 595445 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.0 ['Stratix® 10 FPGAs and SoCs', 'Stratix® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']