Why doesn't i_tx_pll_locked assert after enabling the AN/LT feature when using the E-Tile Ethernet IP for Intel Agilex® 7 FPGA IP? - Why doesn't i_tx_pll_locked assert after enabling the AN/LT feature when using the E-Tile Ethernet IP for Intel Agilex® 7 FPGA IP? Description Due to a problem in E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IP User Guide, when you follow the external hard reset sequence with AN/LT enabled, you will see i_tx_pll_locked remains low when i_csr_rst_n =1'b0. Resolution To work around this problem, release i_csr_rst_n after ninit_done without waiting for i_tx_pll_locked = 1'b1. Custom Fields values: ['novalue'] Troubleshooting 15011226261 False ['E-tile Hard IP for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue No plan to fix ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']