Why are illegally generated clocks reported in the timing report when using the F-Tile PMA and FEC Direct PHY FPGA IP on Agilex™ 7 devices in Quartus® Prime Pro Edition Software v23.4? - Why are illegally generated clocks reported in the timing report when using the F-Tile PMA and FEC Direct PHY FPGA IP on Agilex™ 7 devices in Quartus® Prime Pro Edition Software v23.4? Description Due to a problem in the Quartus® Prime Pro Edition Software v23.4, illegally generated clocks are reported in the timing report when using the F-Tile PMA and FEC Direct PHY FPGA IP on Agilex™ 7 devices in the Quartus® Prime Pro Edition Software v23.4. The following screenshot is an example showing illegally generated clocks in the timing report. This problem is due to the F-Tile PMA and FEC Direct PHY FPGA IP generating timing constraints for tx_clkout2 and rx_clkout2 ports that have not been enabled in the IP. Resolution To work around this problem, enable the tx_clkout2 and rx_clkout2 ports in the F-Tile PMA and FEC Direct PHY FPGA IP even if not used. Alternatively, ignore those illegally generated clocks in the timing report. This problem has been fixed in the Quartus® Prime Pro Edition Software v24.1. Custom Fields values: ['novalue'] Troubleshooting 15015682155 False ['F-Tile PMA/FEC Direct PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']