Agilex5: How to use a GTS refclk to clock the FPGA fabric? - Agilex5: How to use a GTS refclk to clock the FPGA fabric? I tried to use the GTS System PLL configured with FABRIC_USE_CASE and ref clock frequency to 156.25MHz, C1 enable and selected 101.768092 MHz from the C1 output frequency menu but this results in the following error: Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 I/O pad(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. Error (175019): Illegal constraint of I/O pad to the location PIN_AT120 Info (14596): Information about the failing component(s): Info (175028): The I/O pad name(s): pad_spf_refclk_p Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error (175006): There is no routing connectivity between the I/O pad and destination I/O input buffer Info (175027): Destination: I/O input buffer pad_spf_refclk_p~input Error (175022): The I/O pad could not be placed in any location to satisfy its connectivity requirements Error (175022): The destination I/O input buffer could not be placed in any location to satisfy its connectivity requirements Info (175029): 1 location affected Info (175029): PIN_AT120 PIN_AT120 is REFCLK_GTSL1C_RX_P on the Arrow AXE5-Eagle board. I also tried to use the regular IOPLL but it results in the same error. How can I use the GTS refclk to clock the FPGA fabric? Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? Thank you Frank, The problem appears to be that the output clock of the System PLL was not connected. In the larger design it appears to be due to a problem with a generate statement which also connect the different clocks to different blocks. In the minimal design I removed most of the logic but forgot to connect it to the LED register. Sorry about that. If I connect the LED register, drive the ready pin to 1 and include the DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_100MHZ setting it builds at my end. Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? FvM Appreciate your help on this case. Your explanation and elaboration are very helpful. zener Feel free to test out Frank's later recommendation which is compiling correctly and keep us posted if there is any inquiry. Thank you. Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? Hi, posted minimal design doesn't work because it doesn't connect system PLL output to anything, thus the PLL is discarded during synthesis. Modified top.sv respectively assign {//pad_rled0, pad_gled0, pad_bled0, pad_rled1, pad_gled1, pad_bled1, pad_rled2, pad_gled2, pad_bled2, pad_rled3, pad_gled3, pad_bled3} = 11'o213; //12'o4213; assign pad_dbg_tx = pad_dbg_rx; assign pad_rled0 = clk101p768092; assign clk101p768092_ready = 1'b1; Connecting the PLL reveals another error. The fact that you never got to this point suggests that the PLL wasn't implemented in your design, e.g. due to missing connectivity. Error(22849): Intel FPGA IP instantiated in the design requires the DEVICE_INITIALIZATION_CLOCK option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ, or OSC_CLK_1_125MHZ. This assignment is missing in the QSF file. Added set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_100MHZ Get still complains about missing constraints, but design basically compiles now. Regards Frank P.S.: Don't know, if DEVICE_INITIALIZATION_CLOCK is actually required to run system_pll. GTS PHY itself needs it according to device handbook. Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? I've attached a zip file for a minimal project. On Linux it can be extracted using: mkdir /tmp/fpga-forum cd /tmp/fpga-forum unzip ~/Downloads/project.qar.zip quartus_sh --restore project.qar cd /tmp/fpga-forum/scratch/fpga/builds/tests/axe5-eagle/80902c4/quartus quartus project.qpf & Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? Instatiation looks normal, context matters however, connected pins and clock target, possibly selected device. Can you provide a stripped-down design (preferably as zipped .qar) that generates the error? Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? /Td6WFoAAATm1rRGAgAhARYAAAB0L+Wj4GHACYtdAB4Py4cR2M5mkQ+DHsr9ezPUf+m32ibnrjdi /qdvpGOZ/+JnSl5SyBgVcQoU85XqZaOFeiXhHxxEXTK5EY88Bv3OaEFjRxf+V7xPyLKvalNWQp03 qqafjW+WplV5O9vfFlu0EWCXJVcpK4UK5gPadkaYv01YLaG4xBiwFSxScQfr5oXjbsdZy2NcypT5 UCaH8QkbK9P0IDEt2i06PicQb2Itw5dpv6F/EecdhLQm/rYJSGKg4C5jm4Dv86xOGHkkNTZYGCpO cMi794uZdNjVJrwr6c0MNu7A8fD5JQ4TIedyuAB+B7qVHaAD0OKseL4I/Yn/8gwlzE4+vKgVdtg7 iLNJMTTHjBtPSsKODaLv4W4icVfw8sqGzRnX33B2yTsfvXJMuRwiBKsp7FXCKOOJNYy1Q2qQPTB0 ZpsIX1MZ1Xp8HT5K7dERDO+30sNyeW2i3gPjRdSPuZ55FJPJEWXxDaCpLPielIhzo6TDGpvrud/S ltQNnv6c0hjVHH7TSdAQ+9PbRdhQzXu+uNxu2GB80JpPgn/By4WgoilBSAtaj1Ki1Y+ljEEPC6ti 83UCx/ASsUu97DKVfasNe4Nn/2iLupQEEwTPTEG/BV+j9WksT9c9QbF20AfJW1ZGN72lKmzDfiLp s6IDN5H9ARWVbaC5CYnQkuGSOjRJnCoAksxIiAeT6zbPree1cFmBWKilLhuql6BPwB5/vT7Ta1BM WtuSdSH7JYaVbmgMYj19iHSk1abnx0S2M8l5luL4oxnMx2jX1DFJyEMSyqgSU732wm2o81uML6QO tIizWGzmwrTmX6dQEDNyTEsrF3JGdXCE4Y/A57xeytXhDpNYoTi102qs7YgKxKjbJv4Bo77AQy7o 3OE9C5m6uulgtv04fhsKVeh42tOqRACeGldlnwTkE/W6o04YCDODSuFIyw6bUDoOcDP2qUG6K5bt ERdAvqnuxAzhgimA/gXtrIgKpV6C7Vvf0XlwdJufeXKLL5uo/0GPVQU+RMU9VK+ZqDK7KxfBK1yu CpqTFbk69OcMrxPduZjNGaEpfezP8m3yQfIz1FAaJvrR8NnO0hWKRwB3anksuTsLu2UzVX8mM6Cw 79AZopQbCWjTZYqiLoZfqAH84i2xa5EYMf9brjTSE9NDqV83AKEcrPwibuH5EK0GhNVRTbrBJL9D yMQqa647erKkooW+9YVvz2ZISQCkX0iu4iqT3YowJxKVMdah9YH9OwHC33qg++b/Se5JPFKzDg5a ssxj0BsKcf9WfX14wJ4cqQluq5AKtr0QSP5XHBtq9s47FOyhr/qDwFXi8Ir+UCTZtPn27Dg2tvF1 cq78WN+4ftl03MBgZM0L2RF8iM7w7dM6sLsVELq1nbYe7QwzUHvhgTwTnbIN6p4PRzZfr79wL2lT 529XKrFdcB6S1VEIY/vRa7HwqlJ0Hgc7NDUN6Zuy7Us9HzsHJ+OqUaNtMMhcEWoNNwh7ZmVrkCTR jL1OhebUTn0Jgy6et+PbPIrxHuMvY/wCo57qrkNR8DX15CCRaPfTzUCpu78vhBb/GjWQ27O7AtOl 6V8eTzn+Kt+TcA6rApL8FnE0aUpGGeI9SvNHa99wLgbq+f7m+nuENMz1o8NXgffy0Ctte11+8fSK AqhAvDprKQeYC+4GksZR9mbj3lUaV/BlFfheobBWOi4QXy+e2dSsFi3nqs6DS6aUKs/yWp/ZlADq Sknm5crJ+Gsk+hcqKf4OVA7OZ8F9fXMDQ4r6THKKZiqLoHi8uhztZX0VQW53VPDHDx1AcRoEddht 6suFt8oNqTAoMyZvdvZLihdepIOLVgpKDXi37BLdSPBeIxJeG083op9N/XSzGCjBZ0Bnd/lg/ylq vTQ4gWlvGQN710WxI0iCazHKKH/lTAnMTjF2JQQKhyqi1RF1Z+HG8NkGfw4GABUc41EH7xz0bisq NgKP/Q8TOj/V6FpumJshUCR6R6ZzRCVlbBES+0XeUVqcZW8mw31UmH0di1Mku2DXI7HBG9EuBNy/ EsW6uyy5lZaBpcjNcAbhLOzxGv25pxkxph4daQ4MI3OSeRacXS7jBRQPjmaJWwEh3omGIvFMhEyQ 7TJJSkcS+VgeMdFMJrsNsCTErO73xzCnGIwTUyEqhIcprqskFf6Fsl6kHg+A1QQxw2+aowWgOMNy 7Nr78wH/nFCd6Bjq4fnlM7hT8HBieBb6JckduZnp6oCiXWOfejx8N0LO6bh94kUUnFyb12t507RA ZqxWWzfU32qVQaCrxYV/VutqGPGWjL/q+sTPl9StbX7K4VxKjwFPYINyGQZ8+TF4lUcwKTy3Nn7o oQbH4QkOiiBlrD+NKDXDeYF3Fc7XiVWiGNh9S/cqC5djdlfN8XKUluB+SOUtCDBOrfoNhWMJj7MY 8Wtdn3sdboxoP/2K8ixWRPIEVHOwJ5QvqYUWx/iDPD6xE9ggpgkSDHskXng0aBWPs2bTXLYk6Z5e mSssoxBJNsgZ8UH/mFP0OwYKcvUrsECifkIZC8I8G/7RvzGXnYIuqSwgA7MnKZFEx76snseO3QFn /Y3O3pHvGafSAnysCklVcYZ/uPEhGgg0OuBSNCRGd8rCekhr3IN39mqG01THnLjTcYo56s6SgZGU hUJgbSlD4Jzi/H6rfu3OxS0AWKxK5qm8ORVPsy0d8KLfBk1Yv5N6Gn6LF26juPQoe0aNFswyLtSX VUmtKl3YcprlgJa6qT44l/+eKkJsiZu4BNw3eKUkhpUpl7EO61BCT+qdn7g4+29bGY9MHGcp4LVh BlnMEUT2/SGMSRQa5ZOif0y6zdy7jqJNPsIXWwog5SNGjuG7ysiCrXsylFKzVcc3dAvFmsHW+WWV fiacxnZL+bt1nI6FMZYMhJfiOPzEMnqweh9bIwcIOBBiYDkwxd+O/II4JQe4Tn9dx3bQu+FgS89q vn0fNkAuNYuDN6gzpo+ML1mrZIwv76J+sseH+8Wen+gdbMKYYZdHYfVJuY6ouWd0axUsEJ+0YKVw hK1pKwlcxnJfJMZ04EJAeBCjIfqTkkjaolsVXPPAiWgzrw+rtGcVDHBnDn4Cf8lfHs4v79kQdGwl UF/VoFvT783F/IO+su5hsndKi7GcxBlxiUXy01uqrbN5jqk9hI88DI4WT9LDU2UIl4tL89/4uW4N yLNBdulSkDvJuHsXZk+DVM+MHICQH0CC7hmKqBLUIF/QvbSThgYIZ5pS93k81PinLUPl0B9czy+2 dhpg29Qb3A7puNBn/t+FAQHDBDM+PpoAABbVdoII0vKKAAGnE8HDAQDiiA+kscRn+wIAAAAABFla Pasting the above into 'cat | base64 -d | xz -dc > gts_system_pll.ip' should result gts_system_pll. ip with an md5sum of e0eeb0ab0cd45da5eb19b385cef0ca56. Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? logic clk101p768092; logic clk101p768092_lock; logic clk101p768092_ready; gts_system_pll u_gts_system_pll (.o_pll_lock (clk101p768092_lock), .o_syspll_c0 (), .o_syspll_c1 (clk101p768092), .i_refclk (pad_spf_refclk_p), .i_refclk_ready (clk101p768092_ready)); This is the instantiation of the gts_system_pll.ip Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? I left the C0 port unconnected in my last test and only connected C1 as the documentation states: "Only available when Use case of system PLL is set to FABRIC_USE_CASE. When On, there is an output port C1 for FPGA core fabric use.". However, earlier I tried to use the C0 for the fabric (i.e. just clock a simple counter), but it resulted in the same error. Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? Hi, I did a test with c0 output clock. How do you connect c0 in your test? I see that c0=322.265625, c1=101.768092 is accepted. But I neither get the reported error when using c1 clock in FPGA fabric. Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? Thank you for the feedback. I'm not able to manually enter any frequency in the field, only select from the dialog box as shown below: Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? Hi, FABRIC_USE_CASE compiles for me with 100 or 101.875 MHz output frequency. Chosen 101.768092 MHz can't be implemented with 156.25 MHz reference frequency. Regards Frank Replies: Re: Agilex5: How to use a GTS refclk to clock the FPGA fabric? BTW This is using Quartus version 26.1.0 Build 110 03/26/2026 SC Pro Edition.