When using the Arria V GZ and Stratix V Hard IP for PCI Express in multiple packets per cycle mode, why are the signals rx_st_bardec2 and rx_st_bar2 not created? - When using the Arria V GZ and Stratix V Hard IP for PCI Express in multiple packets per cycle mode, why are the signals rx_st_bardec2 and rx_st_bar2 not created? Description Due to a problem in the IP generation, these signals are not automatically exported when mutliple packets per cycle is checked. Resolution Export the signals rx_st_bardec2 in altpcie_sv_hip_ast_hwtcl.v to the top level output of rx_st_bar2 when using multiple packets per cycle, as shown below: output [7:0] rx_st_bar2, assign rx_st_bar2 = rx_st_bardec2[7:0]; Related Articles Why are rx_st_sop, rx_st_eop, tx_st_sop and tx_st_eop only a single bit wide when Enable multiple packets per cycle was set when configurating the Arria 10 Avalon-ST Interface for PCIe Hard IP in Gen3 x8 mode? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']