Component Editor might incorrectly generate validation errors if port widths are set to HDL expressions - Component Editor might incorrectly generate validation errors if port widths are set to HDL expressions Description If you use Qsys to generate a Block Symbol File ( .bsf ) for schematic design entry, the ports of the generated symbol may appear in any order. The order of the ports might change if you regenerate the file. Resolution If you use a schematic to instantiate your Qsys system, you must regenerate a .bsf symbol and reconnect the signals in the Block Diagram File ( .bdf ) each time you change the top-level signals of your Qsys system. If you do not change the top-level signals of the Qsys system, you can turn off symbol generation and reuse the previously generated symbol in your .bdf . Alternatively, use a VHDL or Verilog top-level design file to instantiate your Qsys system. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']