IP Compiler for PCI Express Endpoint in Disable State Does Not Complete Sending Final TS1 Before Transmitting Electrical Idle - IP Compiler for PCI Express Endpoint in Disable State Does Not Complete Sending Final TS1 Before Transmitting Electrical Idle Description If an endpoint receives TS1s with the Disabled Bit set, the endpoint enters the disable state and transmits a sequence of TS1s followed by electrical idle. However, when the IP Compiler for PCI Express endpoint transmits electrical idle, it cuts short the final TS1. A PCI Express link partner might issue a TS ordered set length error in response to the truncated sequence. This issue affects all IP Compiler for PCI Express endpoint variations with hard IP implementations generated with SOPC Builder. Resolution This issue has no workaround. This issue will be fixed in a future version of the IP Compiler for PCI Express. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']