Where are "second address chained" bits in both receiver and transmitter descriptor registers in Cyclone® V/Arria® V SoC Ethernet Media Access Controller assigned? - Where are "second address chained" bits in both receiver and transmitter descriptor registers in Cyclone® V/Arria® V SoC Ethernet Media Access Controller assigned? Description The “Second address chained” bits in receiver and transmitter descriptors are RDES[14] and TDES1[20] respectively. The DMA controller section of the Cyclone® V/Arria® V Hard Processor System Technical Reference Manual version 15.1 and earlier incorrectly state RDES[24] and TDES1[24]. Resolution This problem will be fixed in future release of the Cyclone® V/Arria® V Hard Processor System Technical Reference Manual. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']