Why does the PCIe x8 core's RX buffer credit allocation change values after I Finish generating my PCIe core in the Qsys system? - Why does the PCIe x8 core's RX buffer credit allocation change values after I Finish generating my PCIe core in the Qsys system? Description You may observe after reopening the PCIe® core in your Qsys system, that the Buffer Configuration credit allocations are diffent than the configured values. This is observed when using a x8 configuration. This is a known bug scheduled to be fixed in a future release of the Quartus® II software. Resolution The workaround for this issue is to change the default specified values in the Qsys system top-level RTL file, specifically the PCIe instantiation parameter definition. This is found in <qsys_system_name>.v file and in pcie instantiation template <qsys_system_name>_pcie_hard_ip_0. Default defined in Qsys PCIe instantiation: .vc0_rx_flow_ctrl_posted_header (17), .vc0_rx_flow_ctrl_posted_data (91), .vc0_rx_flow_ctrl_nonposted_header (20), .vc0_rx_flow_ctrl_nonposted_data (0), .vc0_rx_flow_ctrl_compl_header (0), .vc0_rx_flow_ctrl_compl_data (0), Change the above values to those observed in MegaWizard™ Plug-In Manager PCIe core GUI for the configuration you are using. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']