Why do I see a read data mismatch in the clk_tx_div_khz register when simulating the F-Tile Ethernet FPGA Hard IP by enabling the ETH_SIM_SPEED option? - Why do I see a read data mismatch in the clk_tx_div_khz register when simulating the F-Tile Ethernet FPGA Hard IP by enabling the ETH_SIM_SPEED option? Description Due to a problem in the Quartus® Prime Pro Edition software version 24.1, you may see a read data mismatch in the clk_tx_div_khz register when simulating the F-Tile Ethernet FPGA Hard IP with enabling ETH_SIM_SPEED option enabled. This problem does not occur in simulation when the ETH_SIM_SPEED option is not enabled, and does not occur with hardware. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.1. Custom Fields values: ['novalue'] Troubleshooting 16023377516 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']